Here’s another quick project: Below are interactive current-voltage characteristic curves for an n-channel MOSFET. These are based on the Shichman-Hodges model (also known as square-law model or SPICE level 1 model).

Move the sliders to interact!

Gate-Source Voltage \(\nu_{GS}\) (V): 1

Threshold Voltage \(V_{t}\) (V): 0.5

eff. Channel Length \(L_\mathrm{eff}\) (nm): 180

eff. Channel Width \(W_\mathrm{eff}\) (nm): 220

Oxide Thickness \(t_\mathrm{ox}\) (nm): 4.1

Mobility \(\mu\) (cm²/Vs): 290

Channel-Length modulation coeff. \(\lambda\) (1/V): 0.11

The calculations follow those in Chapter 5 of Sedra and Smith, Microelectronic Circuits (2020). For the drain current (\(i_D\)) vs drain-source voltage (\(\nu_{DS}\)) curve of the first figure, we use: \[ i_D = \,\begin{cases} \,\mu \,C_\mathrm{ox} \frac{W_\mathrm{eff}}{L_\mathrm{eff}} \left[ (\nu_{GS} - V_t)\,\nu_{DS} - \frac{1}{2}\nu_{DS}^2 \right] &\mbox{for }\quad \nu_{DS} < \nu_{GS} - V_t \\[13pt] \,\frac{1}{2} \mu \,C_\mathrm{ox} \frac{W_\mathrm{eff}}{L_\mathrm{eff}} (\nu_{GS} - V_t)^2 \,[1 + \lambda (\nu_{DS} - \nu_{GS} + V_t)] &\mbox{for }\quad \nu_{DS} \geq \nu_{GS} - V_t \end{cases} \] with the oxide capacitance \(C_\mathrm{ox} = \frac {\epsilon_\mathrm{ox}}{t_\mathrm{ox}} \) and the permittivity of silicon dioxide \( \epsilon_\mathrm{ox} \). The default parameters on the sliders above are those listed in Sedra and Smith for a standard 180nm CMOS process. The grey-shaded area in figure 1 marks the saturation region. This calculation doesn't include the body effect, so we assume zero bias between source and substrate body.

Consequently, to compute the drain current \(i_{D}\) at saturation (\(\nu_{DS} = \nu_{GS} - V_t\)) in the second figure we use \[ i_{D} = \frac{1}{2} \mu \,C_\mathrm{ox} \frac{W_\mathrm{eff}}{L_\mathrm{eff}} (\nu_{GS} - V_t)^2 \,. \]

The blue marker in figure 2 marks the gate-source voltage \(\nu_{GS}\) chosen on the slider.

Feel free to email me if you have any feedback on this!